Reducing the Power Consumption in Flash ADC Using 65nm CMOS Technology

Document Type : Research Article

Authors

Qazvin Islamic Azad University

Abstract

Today, given the extensive use of convertors in industry, reducing the power consumed by these convertors is of great importance. This study presents a new method to reduce consumption power in Flash ADC in 65nm CMOS technology. The simulation results indicate a considerable decrease in power consumption, using the proposed method. The simulations used a frequency of 1 GHZ, resulting in decreased power consumption by approximately 90% for different processing corners. In addition, in this paper the proposed method was designed using Interpolation technique for purpose of promoting the performance as well as decreasing the class of Chip. The simulation results indicate that the power consumption for Interpolation technique was decreased by approximately 5% compared to the proposed method. On the other hand, we compare the results of the proposed convector with those of convertors frequently referred in other studies. The results show that the power consumption is considerably decreased, using the proposed method.

Keywords

References

[1] B. Razavi, Principles of Data Conversion System Design, Wiley-IEEE Press, 1994.
[2] D. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley &Sons. Inc, 1997.
[3] A. Agarwal and J. Lang, Foundations of Analog and Digital Electronic Circuits, Elsevier. Inc, 2005.
[4] S. Tsukamoto, T. Endo, and W. G. Schofield, "A CMOS 6b 400 Msample/s ADC with error correction," in Proc. IEEE Int. Solid-State Circuits Conf., pp. 152-153, Feb. 1998.
[5] P. Setty, J. Barner, J. Plany, H. Burger, and J.Sonntag, "A 5.7b 350 Msample/s or 6.75b 150 Msample/s Reconfigurable Flash ADC for a PRML Read Channel,"IEEE Int. Solid-State Circuits Conf., pp. 148-149, Feb. 1998.
[6] C. Sandner, M. Clara, A. Santner, T. Hartig, and F.Kuttner, "A 6-bit 1.2-GS/s Low-Power Flash-ADC in 0.13 􀟤m Digital CMOS,"IEEE Journal of Solid-State Circuits, Vol. 40, No. 7, pp. 1499-1505, July 2005.
[7] B. Brandt and J. Lutsky, "A 75-mW 10-B 20-Msample/s CMOS Subranging ADC with 59-dB SNDR,"in ISSCC Dig. Tech. Papers, pp. 322-323,Feb. 1999.
[8] A. Dingwall and V. Zazzu, "An 8-MHZ CMOS Subranging 8-bit A/D Converter,"IEEE J. Solid-State Circuits, Vol. SC-20, pp. 1138-1143, Dec.1985.
[9] A. Abo and P. Gray, "A 1.5-V 10-bit 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,"IEEE J. Solid-State Circuits, Vol. 34, pp. 599-605,May 1999.
[10] K. Nagaraj, H. S. Fetterman, J. Anidjar, S. H.Lewis, and R. G. Renninger, "A 250-mW 8-b 52-MSample/s Parallel-Pipelined A/D Converter with Rduced Number of Amplifiers,"IEEE J. Solid-State Circuits, Vol. 32, pp. 312-320, 1997.
[11] Chun-Cheng Huang, "A Background Comparator Calibration Technique for Flash Analog-to-Digital
Converters," IEEE Transactions On Circuits And Systems, Vol. 52, No. 9, pp. 1732-1740, Sept.2005.
[12] W. Kester, Analog to Digital Conversion,Elsevier,2004.
[13] Marcel J. M. Pelgrom, Analog-to-Digital Conversion, Springer Science, 2010.
[14] F. Maloberti, CMOS Comparators, University of Pavia, 2009.
[15] Jyun-Syong Lai and Zhi-Ming Lin, "A 6-bit 2GS/s Low Power Flash ADC," International Journal of
Engineering and Technology (IACSIT),Vol. 4, No.4, pp. 369-387, August 2012.
[16] M. Panchore and R. S. Gamad, ''Low Power and High Speed CMOS Comparator Design using 0.18
μm Technology,'' International Journal of Electronic Engineering, Vol. 2, No. 1, pp. 71-77,2010.
[17] P. Sunghyun, Y. Palaskas, and M. P. Flynn, ''A 4 GS/s 4b Flash ADC in 0.18μm CMOS,''IEEE Journal of Solide-State Circuits, Vol. 42, No. 9, pp.1865-1872, Sept. 2007.
[18] S. S. Khot, P. W. Wani, M. S. Sutaone, and S. Tripathi, "Design of a 45nm TIQ Comparator for High Speed and Low Power 4-Bit Flash ADC,"International Journal on Electrical and Power Engineering (ACEEE), Vol. 2, No. 1, pp. 7-10,Feb. 2011.
[19] P. Sachin, S. S. Gajre, and V. P. Ghanwat, "Design and Implementation of 4 Bit Flash ADC using Folding Technique in Cadence Tool," International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE),Vol.1,No. 4, pp. 238-241, June 2012.
[20] S. Oza and N. M. Devashrayee, "Folding & Interpolating ADC using Low Power Folding Amplifier," International Journal of Electronics & Communication Technology (IJECT), Vol.1, No.1, pp. 49-54, Dec. 2010.
[21] C. Lane, "A 10-Bit 60 MSPS Flash ADC," IEEE Bipolar Circuits and Technology Meeting, pp. 44- 47, Sept. 18-19, 1989.
[22] P. Kumar and A. Kolhe, "Design & Implementation of Low Power 3-bit Flash ADC in 0.18μm CMOS," International Journal of Soft Computing and Engineering (IJSCE), Vol.1, No. 5,pp. 71-74, Nov. 2011.
[23] D. Ferenci, M. Grozing, F. Lang, and M. Berroth,"A 3 bit 20 GHZ Flash ADC in 65 nm Low Power CMOS Technology," Proceeding of 5th European Microwave Integrated Circuits Conference (EUMA), Paris, France, pp. 214-217, Sept. 27-28,2010.
[24] M. S. Reddy and C. Md. Aslam, "Low Power Flash ADC," International Journal of Computer Applications in Engineering Sciences, Vol. 1, No.2, pp. 108-111, June 2011.
AUT Journal of Modeling and Simulation
Volume 48, Issue 1
June 2016
Pages 39-45

Files

Share

How to cite

Statistics