J. K. Kim, J. Kim, G. Kim and D. K. Jeong, “A fully integrated 0.13-μm CMOS 40-Gb/s serial link transceiver,” IEEE J. Solid-State Circuits., vol. 44, no. 5, pp. 1510-1521, May. 2009.
 N. Da Dalt, E. Thaller, P. Gregorius and L. Gazsi., “A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS,” IEEE J. Solid-State Circuits., vol. 40, no. 7, pp. 1482-1490, Jul. 2005.
 Y. S. Seo, J. W. Lee, H. J. Kim, Ch. Yoo, J. J. Lee and Ch. S. Jeong, “A 5-gbit/s clock and data recovery circuit with 1/8-rate linear phase detector in 0.18-μm CMOS technology,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 1, pp. 6-10, Jan. 2009.
 B. Razavi, “Challenges in the design of high-speed clock and data recovery circuits,” IEEE Commun. Mag.,vol 40, no. 8, pp. 94-101, Aug. 2002.
 N. Da Dalt, “Markov chains-based derivation of the phase detector gain in bang-bang PLLs,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 53, no. 11, pp. 1195–1199, Nov. 2006.
 B. Chun and M. P. Kennedy, “Statistical properties of first-order bang-bang PLL with nonzero loop delay,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 55, no. 10, pp. 1016–1020, Oct. 2008.
 S. Tertinek, J. P. Gleeson, and O. Feely, “Statistical analysis of first-order bang-bang phase-locked loops using sign-dependent random walk theory,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 9, pp. 2367–2380, Sep. 2010.
 S. Cheng, H. Tong, J. Silva-Martinez and A. I. Karsilayan, “Steady-state analysis of phase-locked loops using binary phase detector,” IEEE Trans. Circuits and Syst. II., vol.54, no.6, pp. 474-478, Jun. 2007.
 R. C. Walker, “Designing bang-bang PLLs for clock and data recovery in serial data transmission systems” in Phase-locking in High Performance Systems, B. Razavi, Ed. Piscataway, NJ: IEEE Press, pp. 34–45, 2003.